1. Field of the Invention
The present invention relates to a method of automatically correcting mask pattern data. More particularly, the present invention relates to a method of automatically correcting mask pattern data used in manufacturing a photo mask for a semiconductor integrated circuit.
2. Description of the Related Art
In recent years, a semiconductor integrated circuit, such as a large scale integrated circuit (LSI), a very large scale integrated circuit (VLSI) and an ultra large scale integrated circuit (ULSI) has been highly integrated and densified. The semiconductor integrated circuit has been able to be composed of a million or more transistors in association with the advancement of a higher integration and a higher density. The semiconductor integrated circuit is exemplified as a system LSI. In the system LSI, a system including a central processing units (CPU), memories (ROM, RAM), buffers, a plurality of peripheral devices to carry out various signal processes connected to each other through buses and signal lines, is assembled in one semiconductor chip.
In such a system LSI, as the circuit scale thereof is large, it is impossible to carry out a circuit design directly at a transistor level. Thus, a system design, a function design, a detailed logical design, a circuit design, a layout design and a mask manufacture need to be sequentially executed.
In the system design, CPU, ROM, RAM, a buffer and a plurality of peripheral devices are assumed to be one function block, respectively. The entire operation and configuration of the system are determined so as to obtain the desirable functions. In the function design, the relations among the respective functions and the operations inside the respective function blocks are determined based on the specification determined in the system design. In the detailed logic design, the layout of macro cells to configure the respective function blocks is placed on an IC chip. Here, inner operations of the function blocks are determined by the function design. Then, macro cells are mutually interconnected (placement and routing).
The macro cell is composed of basic logic components and basic logic circuits. The basic logic component is exemplified as a NAND gate and a NOR gate. The basic logic circuit is exemplified as a latch, a counter and a memory which are configured by combining the plurality of above-mentioned basic logic components. In the macro cell, each of the functions is described by using a programming language such as a hardware description language (HDL). The macro cells are registered in a library.
In the layout design, the placement and routing of the cells corresponding to the various basic logic circuits are carried out based on a net list indicating the connection relation among the logic circuits. Then, mask pattern data are manufactured to produce a photo mask. Here, the standard cells and the already-designed modules registered in the library are placed on the chip. Dummy cells are placed in gaps (spaces) between the respective cells so as to embed in the gaps.
The dummy cells are placed, for example, in order to embed in the gaps and consequently control the density of the data, drop the processing amount, improve the yield and insert a capacitance between a power supply and a ground.
Here, the mask pattern data are prepared to produce the many photo masks. Respective mask layers are formed as those mask pattern data. Rectangular regions corresponding to the respective cells and dummy cells are placed in the mask layer. The rectangular regions correspond to open regions of the photo mask.
GFIG. 1 is a view showing a conventional example of the mask pattern data. Assuming that the low Vt transistors (HPTr (High Performance Transistor)) and high Vt transistors (MPTr (Middle Performance Transistor)) are mounted on a substrate. In the HPTr, an ion dose of the ion implantation is relatively low to make a gate threshold voltage (Vt) lower. In MPTr, an ion dose of the ion implantation is relatively high to make the gate threshold voltage (Vt) higher. In this case, two mask layers are used in preparing the mask pattern data for the channel ion implantation of the transistor. One is an ion implantation mask layer (HPTr implantation layer) for forming the low Vt transistor (HPTr) and another is an ion implantation mask layer (MPTr implantation layer) for forming the high Vt transistor (MPTr). Each of two mask layers includes the mask layer for N-channel ion implantation and the mask layer for P-channel ion implantation. As shown in FIG. 1, an N-channel HPTr implantation layer 101, a P-channel HPTr implantation layer 102, an N-channel MPTr implantation layer 103 and a P-channel MPTr implantation layer 104 are used.
Here, in each of the N-channel HPTr implantation layer 101, the P-channel HPTr implantation layer 102, the N-channel MPTr implantation layer 103 and the P-channel MPTr implantation layer 104, a large number of rectangular regions are placed. The rectangular regions correspond to the open regions of the photo masks for forming the cells and dummy cells.
Also, the rectangular regions of each of the implantation layers include rectangular regions 101p and 102p corresponding to the open regions of the photo masks for forming the cells and dummy cells.
Next, while the routing between the cells is carried out, the mask pattern data (artwork data) as the layout design result is verified.
Here, when a design rule check is carried out, in particular, in a multi Vt process, there may be a case that the width of the dummy cell is smaller than the minimum value of the design standard. Thus, a large number of dummy cells are placed which may be possibly judged as a design rule violation. Here, in the multi Vt process, a plurality of kinds of channel ion implantation is carried out in order to form a plurality of kinds of transistors. Each of the plurality of kinds of transistors corresponds to one of a plurality of kinds of the gate threshold voltages (Vt).
That is, the dummy cell is placed based on the outer shape of the cell. Thus, if the design rule violation occurs because the data of the cell includes the data that does not satisfy the design rule, there may be possibly the case that an automatic placement and routing tool cannot solving the violation.
For this reason, a mask layer synthesizing process performs a resizing process on a cell adjacent to the dummy cell which is judged as the design standard violation. In the resizing process, a reducing figure process is carried out after an enlarging figure process. This causes that the dummy cell is absorbed to the adjacent cell. As a result, the design standard violation can be solved.
For example, as shown in FIG. 1, when the rectangular region of the N-channel MPTr implantation layer 103 is placed adjacently to the rectangular region 101p, the resizing process is performed on this rectangular region. The rectangular region 101p is absorbed to this rectangular region. This situation is shown in FIG. 2. FIG. 2 is a view showing a conventional example of the mask pattern data. As shown in FIG. 2, this is referred to as a new rectangular region 103b. 
Also, as shown in FIG. 1, when the rectangular region of the P-channel MPTr implantation layer 104 is placed adjacently to the rectangular region 102p, the resizing process is performed on this rectangular region. The rectangular region 102p is absorbed to this rectangular region. As shown in FIG. 2, this is referred to as a new rectangular region 104b. 
However, this resizing process results in a problem that this requires an enormous processing time and a data storing capacity.
Also, the above-mentioned conventional technique, there may be the case of the residual of the design rule violation which cannot be solved by the resizing process. In this case, the manual modification of the artwork is required at the stage of the mask formation. Therefore, the enormous amount of the modification must be carried out as well as the waste of time and labor occurs on the designing work.
FIG. 3 is a view showing a conventional example of the mask pattern data. As shown in FIG. 3, the residual design rule violation occurs in the case that the rectangular region 101p and the rectangular region 102p are in point contact with each other at a corner (the portion B). Also, as shown in FIG. 2, the residual design rule violation occurs in the case that the rectangular region 101 and the other rectangular region 101 are in point contact with each other at a corner (the portion A) In these cases, during the resizing process, the rectangular regions may return to the original states or the originally necessary portion may be removed. This also causes that the manual modification must be inevitably required.
In conjunction with the above description, Japanese Laid Open Patent Application (JP-A-Heisei 6-318643) discloses a method of resizing process for LSI layout pattern data. In the method of resizing process for LSI layout pattern data, firstly, the resizing process is classified into two cases. One is the case that a pattern is changed in phase. That is, the cell of the pattern is changed in the number of the sides constituting the outline of the cell. Another is the case that the pattern is not changed. Then, the resizing process is carryed out based on the pattern only if it is changed to make the process speed higher.